姓名：蔡懿慈

教育背景工學(xué)學(xué)士 (半導(dǎo)體物理與器件), 清華大學(xué), 中國(guó), 1983;

工學(xué)碩士 (計(jì)算機(jī)應(yīng)用), 清華大學(xué), 中國(guó), 1986;

工學(xué)博士 (計(jì)算機(jī)應(yīng)用), 中國(guó)科學(xué)技術(shù)大學(xué), 中國(guó), 2007.

學(xué)術(shù)兼職清華大學(xué)計(jì)算機(jī)系軟件與理論研究所: 所長(zhǎng) (2008-);

清華大學(xué)計(jì)算機(jī)系分學(xué)術(shù)委員會(huì): 委員 (2008-);

Integration, VLSI of Journal: 編委 (2009-2011);

《半導(dǎo)體學(xué)報(bào)》: 編委 (2009-2011).

研究領(lǐng)域集成電路計(jì)算機(jī)輔助設(shè)計(jì)；集成電路；微電子

研究概況我的主要研究興趣為微電子與計(jì)算機(jī)交叉領(lǐng)域中的IC設(shè)計(jì)優(yōu)化算法與大規(guī)模數(shù)值計(jì)算分析，已經(jīng)從事EDA領(lǐng)域研究工作20多年。近年來，伴隨著Moore定律的發(fā)展，我對(duì)IC設(shè)計(jì)中的互連線時(shí)延和噪聲分析優(yōu)化、大規(guī)模IC供電網(wǎng)絡(luò)并行分析、低功耗物理設(shè)計(jì)優(yōu)化、以及納米工藝下面向可制造性（DFM）設(shè)計(jì)優(yōu)化等一些國(guó)際前沿性問題進(jìn)行了深入的研究。先后參加或主持了國(guó)家“核高基”科技重大專項(xiàng)、973、863、國(guó)家自然科學(xué)基金重大國(guó)際合作、國(guó)家自然科學(xué)基金等多項(xiàng)國(guó)際科研或合作項(xiàng)目。 主要工作分為以下三方面：

1. 對(duì)IC片上供電網(wǎng)絡(luò)的分析和優(yōu)化進(jìn)行了系統(tǒng)和深入的研究：提出了基于GPU的P/G網(wǎng)絡(luò)并行分析快速泊松方法，獲得DAC 2009最佳論文提名獎(jiǎng)，這是大陸學(xué)者首次獲得該項(xiàng)榮譽(yù)；提出了基于三維模型的大規(guī)模P/G網(wǎng)絡(luò)快速分析方法，成果發(fā)表在國(guó)際IC物理設(shè)計(jì)年會(huì)ISPD 2006及國(guó)際期刊Trans. On CAD上；提出了Dcap電容優(yōu)化與布局結(jié)合等一系列P/G網(wǎng)絡(luò)優(yōu)化方法，成果發(fā)表在國(guó)際會(huì)議ICCAD 2009及國(guó)際期刊Trans. On CAS-II國(guó)際期刊上。

2. 對(duì)IC低功耗與時(shí)序物理設(shè)計(jì)優(yōu)化進(jìn)行了研究：提出了性能驅(qū)動(dòng)的功耗關(guān)斷物理優(yōu)化方法，獲得以功耗優(yōu)化為主題的國(guó)際年會(huì)SGLVLSI 2008最佳論文獎(jiǎng)，這是大陸學(xué)者首次獲得該項(xiàng)榮譽(yù)；提出了基于電壓島多供電功耗優(yōu)化方法、時(shí)鐘關(guān)斷功耗優(yōu)化方法等，成果發(fā)表在國(guó)際IC物理設(shè)計(jì)年會(huì)ISPD 2008及國(guó)際期刊Trans. On VLSI上。

3. 對(duì)納米工藝下工藝參數(shù)變化及可制造性（DFM）問題進(jìn)行深入研究：與Synopsys合作提出了基于區(qū)域模型匹配的OPC熱點(diǎn)探測(cè)方法，獲得ICCAD 2006最佳論文提名獎(jiǎng)；提出了一系列面向DFM的布線和優(yōu)化算法，成果發(fā)表在國(guó)際會(huì)議及Trans. On VLSI等國(guó)際期刊上。

國(guó)家“核高基”科技重大專項(xiàng): 先進(jìn)EDA工具平臺(tái)開發(fā) (2008-2010);

國(guó)家自然科學(xué)基金海外青年合作: 考慮工藝參數(shù)變化的IC設(shè)計(jì)優(yōu)化理論與關(guān)鍵技術(shù) (2009-2010);

國(guó)家自然科學(xué)基金: 極大規(guī)模集成電路片上供電網(wǎng)絡(luò)仿真及優(yōu)化 (2008-2010);

國(guó)家自然科學(xué)基金: 納米工藝下集成電路自動(dòng)布線算法研究 (2010-2012).

獎(jiǎng)勵(lì)與榮譽(yù)教育部科技進(jìn)步二等獎(jiǎng)——超大規(guī)模集成電路物理級(jí)優(yōu)化和驗(yàn)證問題基礎(chǔ)研究 (2006);

DAC 2009: 最佳論文提名獎(jiǎng) (2009);

ICCAD2006: 最佳論文提名獎(jiǎng) (2006);

GLVLSI 2008: 最佳論文獎(jiǎng) (2008);

清華大學(xué): 教學(xué)優(yōu)秀獎(jiǎng) (2000).

學(xué)術(shù)成果 Yanni Zhao, Jinian Bian, Shujun Deng, Zhiqiu Kong, Kang Zhao. Constrained Stimulus Generation with Self-adjusting Using Tabu Search with Memory. IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences. Vol.E92-A, No.12, 3086-3093. 2009.

Junbo Yu, Qiang Zhou, Gang Qu and Jinian Bian, Peak Temperature Reduction by Physical Information Driven Behavioral Synthesis with Resource Usage Allocation, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E92-A, (No.12), 3151-3159, 2009.

Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto, Pipeline-Based Partition Exploration for Heterogeneous Multiprocessor Synthesis. IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, Vol.E92-A, No.9, 2283-2294, 2009

Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto, “Exploring Partitions Based on Search Space Smoothing for Heterogeneous Multiprocessor System”. IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, Val. E91-A, no. 9, 2456-2464, 2008.

Tong, Kun, Bian, Jinian, Wang, Haili, “A cooperative universal data model platform for the data-centric electronic system-level design”, Advanced Engineering informatics, val. 22, no. 3, 296-306, 2008.

Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto, “Fast Custom Instruction Identification Algorithm Based on Basic Convex Pattern Model for Supporting ASIP Automated Design”, IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, val. E91-A, no.6, 1478-1483, 2008.

Ming Zhu，Jinian Bian, Weimin Wu： “A novel collaborative scheme of simulation and model checking for system properties verification”, Computers in Industry, special issue: Collaborative Environments for Concurrent Engineering, Elesvier, val.57, no.8-9, 752-757, 2006

Shujun Deng, Jinian Bian, Weimin Wu, Xiaoqing Yang, Yanni Zhao, “EHSAT: An RTL Satisfiability Solver Using an Extended DPLL Procedure”, Proc. 44th Design Automation Conference (DACu201907), San Diego, California, USA, 2007, 588-593

Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng, “A Novel Fixed-outline Floorplanner with Zero Deadspace for Hierarchical Design”, Proc. The 2008 IEEE/ACM International Conference on Computer-Aided Design, (ICCADu201908), San Jose, CA, USA, 16 u2013 23, 2008.

Shujun Deng, Zhiqiu Kong, Jinian Bian, Yanni Zhao, “Self-Adjusting Constrained Random Stimulus Generation Using Splitting Evenness Evaluation and XOR Constraints”, Prof. 14th Asia and South Pacific Design Automation Conference, (ASPDACu201909), Yokohama, Japan, 769 u2013 774, 2009.

Junbo Yu, Qiang Zhou, Jinian Bian, “Peak Temperature Control in Thermal-aware Behavioral Synthesis through Allocating the Number of Resources”, proc. 14th Asia and South Pacific Design Automation Conference (ASPDACu201909), Yokohama, Japan, 85 u2013 90, 2009.

Junbo Yu, Qiang Zhou, Gang Qu, and Jinian Bian, “Behavioral Level Dual-Vth Design for Reduced Leakage Power with Thermal Awareness”, Proc. The 10th Design, Automation and Test, (DATEu201910), Dresden, Germany, 2010. 3. 8-12, pp 1261-1266, 2010

劉大為, 周強(qiáng), 邊計(jì)年. “考慮重疊度和線長(zhǎng)的單元密度平滑方法”, 計(jì)算機(jī)輔助設(shè)計(jì)與圖形學(xué)學(xué)報(bào), 第22卷第4期, 676-681，688, 2010.

趙燕妮, 邊計(jì)年, 鄧澍軍. “利用SMT約束分解方法求解RTL可滿足性問題”, 計(jì)算機(jī)輔助設(shè)計(jì)與圖形學(xué)學(xué)報(bào), 第22卷第2期, 234-239, 2010.

于浚泊, 周強(qiáng), 邊計(jì)年. “考慮熱效應(yīng)的資源數(shù)量分配算法”, 計(jì)算機(jī)輔助設(shè)計(jì)與圖形學(xué)學(xué)報(bào), 第21卷第9期, 2009.

童琨, 邊計(jì)年. “片上系統(tǒng)中事務(wù)級(jí)建模相關(guān)研究綜述”, 計(jì)算機(jī)輔助設(shè)計(jì)與圖形學(xué)學(xué)報(bào), 第19卷第11期, 2007.

劉志鵬, 邊計(jì)年, 周強(qiáng). “高層次綜合中面向功耗優(yōu)化的方法與技術(shù)”, 計(jì)算機(jī)輔助設(shè)計(jì)與圖形學(xué)學(xué)報(bào), 第19卷第11期19(11), 2007.

趙康, 邊計(jì)年, 董社勤. “基于集束式整數(shù)線性規(guī)劃模型的專用指令集自動(dòng)定制”, 計(jì)算機(jī)輔助設(shè)計(jì)與圖形學(xué)學(xué)報(bào), 第19卷第10期, 1229-1234, 2007.

劉志鵬, 邊計(jì)年, 周強(qiáng). “高層次綜合中基于整數(shù)線性規(guī)劃模型的多目標(biāo)功耗優(yōu)化算法”, 計(jì)算機(jī)輔助設(shè)計(jì)與圖形學(xué)學(xué)報(bào), 第19卷第8期, 966-972,2007.

鄧澍軍, 吳為民, 邊計(jì)年. “RTL驗(yàn)證中的混合可滿足性求解”, 計(jì)算機(jī)輔助設(shè)計(jì)與圖形學(xué)學(xué)報(bào), 第19卷第3期, 273-278,285, 2007.

邊計(jì)年, 薛宏熙, 蘇明, 吳為民. 數(shù)字系統(tǒng)設(shè)計(jì)自動(dòng)化. 第2版. 清華大學(xué)出版社, 北京, 2005.

洪先龍, 劉偉平, 邊計(jì)年. 超大規(guī)模集成電路計(jì)算機(jī)輔助設(shè)計(jì)技術(shù), 國(guó)防工業(yè)出版社, 北京, 1998.