著作
出版著作有《數(shù)字系統(tǒng)計(jì)算機(jī)輔助設(shè)計(jì)》、《數(shù)字系統(tǒng)設(shè)計(jì)自動(dòng)化》、《超大規(guī)模集成電路計(jì)算機(jī)輔助設(shè)計(jì)技術(shù)》等。譯著有《VHDL簡(jiǎn)明教程》、《數(shù)字邏輯與VHDL設(shè)計(jì)》、《嵌入式系統(tǒng)的描述與設(shè)計(jì)》等。研究方向
計(jì)算機(jī)與超大規(guī)模集成電路計(jì)算機(jī)輔助設(shè)計(jì)(ICCAD)或稱(chēng)電子設(shè)計(jì)自動(dòng)化(EDA)領(lǐng)域中，系統(tǒng)與行為級(jí)的設(shè)計(jì)方法和軟件工具的研究。目前的研究重點(diǎn)是以片上系統(tǒng)SOC（System on a chip）為對(duì)象的軟硬件協(xié)同設(shè)計(jì)與協(xié)同驗(yàn)證、體系結(jié)構(gòu)與接口綜合、與布圖結(jié)合的高層次與邏輯綜合，以及集成電路芯片物理設(shè)計(jì)算法的研究。目前的在研項(xiàng)目有： 1.國(guó)家自然科學(xué)基金重大計(jì)劃面上項(xiàng)目（項(xiàng)目負(fù)責(zé)人）：多目標(biāo)自適應(yīng)粒度的系統(tǒng)級(jí)劃分與接口綜合算法研究； 2.國(guó)家自然科學(xué)基金重點(diǎn)項(xiàng)目(合作負(fù)責(zé)人)：SOC設(shè)計(jì)的關(guān)鍵技術(shù)研究及傳導(dǎo)語(yǔ)音SOC系統(tǒng)實(shí)現(xiàn)； 3.國(guó)家自然科學(xué)基金重大計(jì)劃面上項(xiàng)目（合作負(fù)責(zé)人）：面向SOC設(shè)計(jì)的高層次綜合與布圖規(guī)劃結(jié)合技術(shù)研究； 4. 973項(xiàng)目（項(xiàng)目負(fù)責(zé)人）：延長(zhǎng)摩爾定律的微處理芯片新原理、新結(jié)構(gòu)與新方法研究：高效率的處理芯片的設(shè)計(jì)、驗(yàn)證與測(cè)試。發(fā)表論文
Ming Zhu,Jinian Bian,Weimin Wu, “A Novel Collaborative Scheme of Simulation and Model Checking for Property Verification”，will appear in: Computers in Industry，SCI，EI2002 Cin-Ngai Sze，Wangning Long，Yu-Liang Wu，Jinian Bian，“Accelerating Logic Rewriting Using Implication Analysis”，In Japan：Transactions on Fundamentals of Electronics，Communications and Computer Sciences (IEICE)，E85-A(12)，2002.12，2725-2736，SCI 626XX，EI 03117394401，INSPEC 7553316 Wu Qiang，Bian Ji-Nian，Xue Hong-Xi，“Scheduling with Resource Allocation for Design Space Exploration in System-level Synthesis”(In English)，Journal of Software ¨ Weiwei Zheng, Weimin Wu, Jinian Bian, “RTL Satisfiability Solving and Property Checking Based on Linear Programming” (In Chinese), Journal of Computer Aided Design and Graphics. (鄭偉偉，吳為民，邊計(jì)年，“基于LP的RTL可滿足性求解和性質(zhì)檢驗(yàn)”，計(jì)算機(jī)輔助設(shè)計(jì)與圖形學(xué)學(xué)報(bào)) ZHU Ming, BIAN Ji-Nian, Wu Wei-Min, “CoSAM: a Collaborative Verification System of Functional Simulation and Model Checking” (In Chinese) Computer Integrated Manufactory System. (朱 明，邊計(jì)年，吳為民，“功能模擬與形式驗(yàn)證相結(jié)合的系統(tǒng)級(jí)協(xié)同驗(yàn)證系統(tǒng)CoSAM”，計(jì)算機(jī)集成制造系統(tǒng)（CIMS）) 2005 Haili Wang, Jinian Bian, Zhihui Xiong, Sikun Li, Jihua Chen, “Hierarchical communication model for interface synthesis in system-on-chip design” (In Chinese)，Journal of Computer-Aided Design and Computer Graphics，17（8），2005.8，1803-1808，EI 05359331579. (王海力，邊計(jì)年，熊志輝，李思昆，陳吉華，“SoC接口綜合的層次化通信模型”，計(jì)算機(jī)輔助設(shè)計(jì)與圖形學(xué)學(xué)報(bào)，17（8），2005.8，1803-1808) ¨ Zhihui Xiong, Sikun Li, Jihua Chen, Haili Wang, Jinian Bian, “Co-design environment supporting platform-based system-on-chip design methodology”, (In Chinese), Journal of Computer-Aided Design and Computer Graphics，17(7)，2005.7，1401-1406，EI 05319278319. (熊志輝，李思昆，陳吉華，王海力，邊計(jì)年，“支持平臺(tái)設(shè)計(jì)方法的系統(tǒng)芯片協(xié)同設(shè)計(jì)環(huán)境”，計(jì)算機(jī)輔助設(shè)計(jì)與圖形學(xué)學(xué)報(bào)，17(7)，2005.7，1401-1406) ¨ ZHU Ming, BIAN Jinian, WU Weimin, “Property classification for system verification on CDFG structure” (In Chinese)，Computer Engineering，31(10)，2005.5，48-50，EI 05249160987 (朱明，邊計(jì)年，吳為民，“基于CDFG和OVL的系統(tǒng)驗(yàn)證性質(zhì)分類(lèi)”，計(jì)算機(jī)工程，31(10)，2005.5，48-50) ¨ 趙康，邊計(jì)年，吳強(qiáng)，薛宏熙，“C語(yǔ)言系統(tǒng)描述的HCDFG-II實(shí)現(xiàn)”，計(jì)算機(jī)工程與科學(xué) 27(4)，2005.4，80-83 ¨ 劉志鵬，邊計(jì)年，王云峰，薛宏熙，“面向SOC系統(tǒng)設(shè)計(jì)的層次化CDFG的擴(kuò)展”，計(jì)算機(jī)工程與科學(xué)s based on a new CDFG format for granularity selection in hardware-software partitioning” (In Chinese), Journal of Computer-Aided Design and Computer Graphics，17(3)，2005.3，387-393，EI 05169051874 (吳強(qiáng)，王云峰，邊計(jì)年，薛宏熙: “軟硬件劃分中基于一種新的層次化控制數(shù)據(jù)流圖的粒度變換”，計(jì)算機(jī)輔助設(shè)計(jì)與圖形學(xué)學(xué)報(bào),17(3)，2005.3，387-393) 2004 ¨ Zhihui Xiong, Sikun Li, Jihua Chen, Haili Wang, Jinian Bian, “Hierarchical platform-based SoC system design method”，Acta Electronica Sinica，32(11)，2004.11，1813-1819，EI 05048806862(熊志輝，李思昆，陳吉華，王海力方法”, 電子學(xué)報(bào), 32(11)，2004.11，1813-1819) ¨ “Multi-way hardware-software partitioning algorithm based on abstract architecture template” (In Chinese)，Journal of Computer Aided Design & Computer Graphics，16(11)，2004.11，1562-1567，EI 05038790248，INSPEC 8353409（吳強(qiáng)，邊計(jì)年，薛宏熙，“ATMP: 基于抽象體系結(jié)構(gòu)模板的多路軟硬件劃分算法”，計(jì)算機(jī)輔助設(shè)計(jì)與圖形學(xué)學(xué)報(bào)，16(11)，2004.11，1562-1567） ¨ Yawen Niu, Qiang Wu, Jinian Bian, Hongxi Xue, “HCDFG-II - A representation of control/data flow graph for C language system specification”(In Chinese)，Journal of Computer Aided Design & Computer Graphics，16(11)，2004.11，1547-1552，EI 05028786279，INSPEC 8334598（牛亞文，邊計(jì)年，吳強(qiáng)，薛宏熙， “HCDFG-II——面向C語(yǔ)言系統(tǒng)描述的控制/數(shù)據(jù)流圖表示”，計(jì)算機(jī)輔助設(shè)計(jì)與圖形學(xué)學(xué)報(bào) for Finite State Machine”(In English)，Journal of Computer Science and Technology (JCST)，19(5)，2004.9，729-733，SCI 857RY，EI 04428412745，INSPEC 8312012 2003 ¨ 聶江波，邊計(jì)年，薛宏熙，吳為民，朱明，“基于模塊的層次化模型判別”，微電子學(xué)與計(jì)算機(jī) 2003.12 64-67 ¨ 曹秉超，邊計(jì)年，“順序蘊(yùn)含圖的狀態(tài)編碼方法”，計(jì)算機(jī)工程與應(yīng)用 39(30)，2003.10 79-81 ¨ 朱明，邊計(jì)年，薛宏熙 軟硬件協(xié)同驗(yàn)證系統(tǒng)平臺(tái)間通訊設(shè)計(jì)，計(jì)算機(jī)工程與應(yīng)用 39(27)，2003.9 122-124 2002 ¨ 朱明，邊計(jì)年，薛宏熙，擴(kuò)展的高層次行為描述內(nèi)部模型，計(jì)算機(jī)工程與應(yīng)用，38(16)，2002，204-206 ¨ 趙建洲，朱明，邊計(jì)年，薛宏熙 SOC系統(tǒng)中C到VHDL的轉(zhuǎn)換，計(jì)算機(jī)工程與應(yīng)用 38(16)，2002，12，188-190 ¨ 劉建華，楊勛，邊計(jì)年，薛宏熙，“嵌入系統(tǒng)中斷控制器的設(shè)計(jì)”，計(jì)算機(jī)工程與應(yīng)用 38(1)，2002，1，125-127 2001 ¨ 楊勛，邊計(jì)年，洪先龍，薛宏熙，“面向片上型系統(tǒng)軟硬件協(xié)同驗(yàn)證平臺(tái)的研制”，軟件學(xué)報(bào)Journal of Software，12(增刊)，2001.6，202-207，EI 02036826714 ¨ 范軼平，貝勁松，邊計(jì)年，薛宏熙，洪先龍，“一個(gè)有效的針對(duì)同步時(shí)序電路VHDL設(shè)計(jì)的模型判別器: VERIS”，計(jì)算機(jī)輔助設(shè)計(jì)與圖形學(xué)學(xué)報(bào)Journal of Computer Aided Design & Computer Graphics，13(6)，2001.6，485-489，EI 01336615796，INSPEC 6973523 2000 ¨ 邊計(jì)年，“底層相關(guān)的VLSI高層次設(shè)計(jì)策略”，計(jì)算機(jī)輔助設(shè)計(jì)與圖形學(xué)學(xué)報(bào)Journal of Computer Aided Design & Computer Graphics，12(11)，2000.11，827-829，EI 00125456525，INSPEC 6799823 ¨ 朱明，邊計(jì)年，薛宏熙，“利用變量序過(guò)濾算法減小多叉判決圖規(guī)�！�，微電子學(xué) 30(S0)，2000年增刊，2000.10，130-132 ¨ 許靈均，邊計(jì)年，薛宏熙，“用局部等價(jià)替換技術(shù)改善時(shí)延性能”，微電子學(xué) 30(S0)，2000年增刊，2000.10，124-126 ¨ 盧峰，邊計(jì)年，薛宏熙，“結(jié)合OBDD和電路結(jié)構(gòu)的等價(jià)性驗(yàn)證算法”，微電子學(xué) 30(S0)，2000年增刊2000.10 121-123 ¨ 楊勛，薛宏熙，邊計(jì)年，“微處理器模型CE及其驗(yàn)證方法”，微電子學(xué) 30(S0)，2000年增刊，2000.10，156-158 ¨ 徐正生，曹霆，邊計(jì)年，薛宏熙，“時(shí)延驅(qū)動(dòng)的多級(jí)邏輯綜合研究”，計(jì)算機(jī)應(yīng)用 2000年增刊，2000.9 168-170 ¨ 范軼平，貝勁松，邊計(jì)年，薛宏熙，“符號(hào)模型判別系統(tǒng)的一種實(shí)用反例生成策略”，計(jì)算機(jī)應(yīng)用 2000年增刊，2000.9，165-167， ¨ Long Wang-ning，Min Ying-hu，Bian Ji-nian，Yang Shi-yuan，Xue Hong-xi，“Efficient Heuristic Variable Ordering of OBDDs”，Tsinghua Science and Technology(清華大學(xué)學(xué)報(bào)英文版)，5(2)，2000.6. 221-226 ¨ 龍望寧，吳有亮，邊計(jì)年，薛宏熙，“基于蘊(yùn)涵樹(shù)的冗余添加與刪除技術(shù)”，計(jì)算機(jī)學(xué)報(bào)Chinese Journal of Computers， 23(4)，2000.4，356-362，EI 01015501585，INSPEC 6605609 ¨ 邊計(jì)年，“布圖驅(qū)動(dòng)的邏輯綜合技術(shù)”，中國(guó)學(xué)術(shù)期刊文摘(科技快報(bào)) 6(3)，2000.3， (0003K016)，387-388 1999 ¨ 曹霆，吳彥青，王剛，邊計(jì)年，薛宏熙，“Windows中圖形數(shù)據(jù)傳輸技術(shù)的實(shí)現(xiàn)”，電子技術(shù)與應(yīng)用 25(10)，1999.10. 9-11 ¨ 王志明，邊計(jì)年，龍望寧，薛宏熙，“基于二叉判決圖的邏輯電路形式驗(yàn)證工具”，軟件學(xué)報(bào) 10(增刊)，1999.6. 235-238 TP3-2 ¨ 貝勁松，邊計(jì)年，薛宏熙，龍望寧，洪先龍，“SAS：形式驗(yàn)證中的OBDD變量排序算法”，計(jì)算機(jī)輔助設(shè)計(jì)與圖形學(xué)學(xué)報(bào)Journal of Computer Aided Design & Computer Graphics，11(5)，1999.9，412-416，EI 99114878831，INSPEC 006406117 ¨ 貝勁松，李洪星，邊計(jì)年，薛宏熙，洪先龍，“形式驗(yàn)證中同步時(shí)序電路的VHDL描述到S2-FSM的轉(zhuǎn)換”，計(jì)算機(jī)輔助設(shè)計(jì)與圖形學(xué)學(xué)報(bào)Journal of Computer Aided Design & Computer Graphics 11(3)，1999.5，196-199，EI 99084745239，INSPEC 006278840 1998 ¨ 貝勁松，李洪星，邊計(jì)年，薛宏熙，“BDD在有限狀態(tài)機(jī)驗(yàn)證中的應(yīng)用”，微電子學(xué)與計(jì)算機(jī) 1998年增刊，1998.7 158-161 ¨ 趙方，郭芳，邊計(jì)年，王剛，薛宏熙，“VHDL翻譯型模擬器中函數(shù)功能的實(shí)現(xiàn)”微電子學(xué)與計(jì)算機(jī) 1998年增刊，1998.7，133-135 ¨ 邊計(jì)年，“VITAL─設(shè)計(jì)ASIC模型的VHDL基準(zhǔn)”，計(jì)算機(jī)輔助設(shè)計(jì)與圖形學(xué)學(xué)報(bào)Journal of Computer Aided Design & Computer Graphics，10(2)，1998.3. 161-166，EI 98064254897，INSPEC 006144280 ¨ 邊計(jì)年，陳菁，“V2C++—— 一個(gè)用C++實(shí)現(xiàn)的VHDL 翻譯型模擬器”，計(jì)算機(jī)輔助設(shè)計(jì)與圖形學(xué)學(xué)報(bào)Journal of Computer Aided Design & Computer Graphics，10(2)，1998.3. 167-172 EI 98064254898 INSPEC 006144281 1997 ¨ 邊計(jì)年，盧峰，郭芳，“適應(yīng)調(diào)試功能的VHDL模型及模擬算法”，計(jì)算機(jī)學(xué)報(bào)Chinese Journal of Computers，20(11)，1997.11，996-1002，EI 98034142626，INSPEC 005851162 1995 ¨ 邊計(jì)年，移容樹(shù)，“VHDL預(yù)定義算符的功能實(shí)現(xiàn)及其數(shù)據(jù)類(lèi)型的相容性”，微電子學(xué)與計(jì)算機(jī) 1995年增刊[1995.7]，11-13 ¨ 邊計(jì)年，郭芳，“VHDL層次化結(jié)構(gòu)模型及其確立算法”，微電子學(xué)與計(jì)算機(jī)，1995 年增刊[1995.7] ，8-10 ¨ 蘇明，薛宏熙，邊計(jì)年，“VHDL集成設(shè)計(jì)環(huán)境”，微電子學(xué)與計(jì)算機(jī)，1995年增刊[1995.7]，1-3 1994 ¨ 王慶生，薛宏熙，邊計(jì)年，“圖文混合編輯器中VHDL源描述的自動(dòng)生成”，計(jì)算機(jī)工程，1994年專(zhuān)刊[1994.6] 1991 ¨ 邊計(jì)年，盧勤，呂昌，劉渝，連永君，“一個(gè)功能較強(qiáng)的交互式混合級(jí)邏輯模擬工具SIM”，計(jì)算機(jī)輔助設(shè)計(jì)與圖形學(xué)學(xué)報(bào) for Power Optimization Using Multiple Voltages in Data Path Synthesis”, 2005 6th International Conference on ASIC Proceedings, ASICONu201905, Shanghai, 2005.10.17-20, 902-905 ¨ Shaohe Wu, Minchuan Chen, Weimin Wu, Jinian Bian, “RTL Property Checking Technology Based on ATPG and ILP”, 2005 6th International Conference on ASIC Proceedings, ASICONu201905, Shanghai, 2005.10.17-20, 890-893 ¨ Minchun Chen, Weimin Wu, Jinian Bian, “RTL Satisfiability Solving Using an ATPG based Approach”, 2005 6th International Conference on ASIC Proceedings, ASICONu201905, Shanghai, 2005.10.17-20, 910-913 Tao Liu, Wei-Ming Wu, Yu-Liang Wu, Ji-Nian Bian, “Hexagon/Triangle Packing Using Improved Least Flexibility First Principle”, 2005 6th International Conference on ASIC Proceedings, ASICONu201905, Shanghai, 2005.10.17-20, 828-831 Zhuoyuan Li, Haixia Yan, Xianlong Hong, Qiang Zhou, Jinian Bian, Hannal H. Yang, Vijay Pitchumani, “Design Tools for 3D Mixed Mode Placement”, 2005 6th International Conference on ASIC Proceedings, ASICONu201905, Shanghai, 2005.10.17-20, 796-799 Bin Liu, Yici Cai, Qiang Zhou, Jinian Bian, Xianling Hong, “Decomposition for Power Gating Design Automation in Sequential Circuits”, 2005 6th International Conference on ASIC Proceedings, ASICONu201905, Shanghai, 2005.10.17-20, 862-865 Weiwei Zheng，Weimin Wu，Jinian Bian，“Hierarchical Property Checking for RTL Circuits by LP-based Satisfiability Solving”，The 6th Workshop on RTL and High level Test Symposium，WRTLTu201905，Harbin，2005.7. 213-218 Di Wang，Weimin Wu，Weiwei Zheng，Jinian Bian，“Model Checking of A DLX Microprocessor Design By Exploiting Modular Hierarchy，Synthesis System”，Proceedings of International Conference on Computer Aided Industrial Design and Conceptual Design，CAID&CDu201905，Delft，Nederland，2005.5. 601-606，ISTP BCT62 Yawen Niu，Jinian Bian，Haili Wang，“CGEM: A Communication Graph Extraction Methodology Based on HCDFG for Channel Mapping in System Level Design”，Proceedings of International Conference on Computer Aided Industrial Design and Conceptual Design，CAID&CDu201905，Delft，Nederland，2005.5. 696-701，ISTP BCT62 Liang Zhu，Haili Wang，Jinian Bian，“A Novel Method of Generating Transaction-level Model Based on Transformation Techniques”，Proceedings of International Conference on Computer Aided Industrial Design and Conceptual Design，CAID&CDu201905，Delft，Nederland，2005.5. 768-773，ISTP BCT62 Rongjun Mu，Jinian Bian，Yu-liang Wu，Wai-Chung Tang，“Further Minimization of Bdds for LargeCircuits With Xor/Xnor Recognition”，Proceedings of International Conference on Computer Aided Industrial Design and Conceptual Design，CAID&CDu201905，Delft，Nederland，2005.5. 551-555，ISTP BCT62 Wenjun Wang，Yunfeng Wang，Jinian Bian，“A Congestion Driven Re-Synthesis Method after floorplannig”，2005 (3st) International Conference on Communications，Circuits，and Systems and West Sino Exprositions Proceedings，ICCCASu201905，Hong Kong，2005.5. 1220-1224，ISTP BCZ13，INSPEC 8623662, IEEE xplore Jianfeng Huang，Jinian Bian，Zhipeng Liu，Yunfeng Wang，“Power optimization in data-path scheduling and binding with multiple supply voltages and threshold voltages by simulated annealing”，2005 (3st) International Conference on Communications，Circuits，and Systems and West Sino Exprositions Proceedings，ICCCASu201905，Hong Kong，2005.5. 1370-1374，ISTP BCZ13，INSPEC 8623694, IEEE xplore Haili Wang，Jinian Bian，Qiang Wu，Yunfeng Wang，“iTuCoMe: HCDFG-based Incremental Tuning HW/SW Codesign Methodology for Multi-level Exploration”，Procedings of The 9th International Conference on Computer Suppoted Cooperative Work in Design，CSCWDu201905，Coventry，UK，2005.5. 978-983，ISTP BCO78，INSPEC 8588021，IEEE Xplore Jianzhou Zhao，Jinian Bian，Weimin Wu，“Cooperation of SMV and Jeda for the Property Checking of Mixed Control and Data Intensive Designs”，Procedings of The 9th International Conference on Computer Suppoted Cooperative Work in Design，CSCWDu201905，Coventry，UK，2005.5. 1024-1028，ISTP BCO78，INSPEC 8588029，IEEE Xplore Yunfeng Wang，Jinian Bian，xianlong Hong，“Interconnect Modeling Approach for SOC Design”，2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings，ICSICTu201904，Beijing，2004.10. v.II，1400-1403 EI 05299218069，ISTP BBR18，INSPEC 8510606 Jianzhou Zhao，Jinian Bian，Weimin Wu，“PFGASAT-a Genetic SAT Solver Combining Partitioning and Fuzzy Strategies”，Proceedings of the 28th Annual International Computer Software and Applications Conference，COMPSAC 2004，Hong Kong，(28th) 2004.9，108-113，EI 05219121849，INSPEC 8303524，IEEE xplore，ACM lib Weimin Wu，Ming Zhu，Jianzhou Zhao，Jinian Bian，“AL/RTL Co-Modeling And General Test Generation”，2004 International Conference on Communications，Circuits and Systems，ICCCAS2004 (2nd)，Chengdu 2004.6. 1329-1333，EI 05038790248，ISTP BBC53，000224820400291，INSPEC 8097931，IEEE xplore Zhu Ming，Bian Jinian，Wu Weimin，“A Novel Collaborative Scheme of Simulation and Moddel Checking for Property Verification”，Proceedings of 8th International Conference on Computer Supported Cooperative Work in Design，CSCWDu201904，Xiamen，(8th，Vol.II) 2004.5. 67-72 ISTP BAN11，000222931800020，INSPEC 8229343，IEEE xplore 2003 Ming Zhu，Jinian Bian，Weimin Wu，Hongxi Xue，“Property Classification for Hibrid Verification”，The 4th Workshop on RTL and High level Test Symposium，WRTLTu201903，(2nd)，Xian 2003.11. 129-132 Jianzhou Zhao，Jinian Bian，Weimin Wu，“ACSAT: A SAT Solver via Solving TSP by ACO”，The 4th Workshop on RTL and High level Test Symposium，WRTLTu201903，Xian 2003.11. 133-137 Weimin Wu，Di Wang，Weiwei Zheng，Jinian Bian，Ming Zhu，Jianzhou Zhao，“Safety Checking By Problem Solving”，The 4th Workshop on RTL and High level Test Symposium，WRTLTu201903，Xian 2003.11. 151-156 Ming Zhu，Jinian Bian，Weimin Wu，Hongxi Xue，“Property Classification for Functional Verification based on CDFG”，Proceedings of the Twelfth Asian Test Symposium，ATSu201903，(12th)，Xian 2003.11，503 ISTP BY38Z 000189157300092，INSPEC 7905635，IEEE xplore ¨ Haili Wang，Qiang Wu，Jinian Bian，Zhihui Xiong，Jihua Chen，Sikun Li，“A Novel Virtual-Real Component Synthesis Approach in SoC Design”，8th International Conference on CAD/Graphics，OCT 29-31，2003 CAD/ GRAPHICS TECHNOLOGY AND ITS APPLICATIONS，PROCEEDINGS，CAD/Graphicsu201903，Macau 2003.10. 151-156，ISTP BAY65 000224243000023 Qiang Wu，Yunfeng Wang，Jinian Bian，Hongxi Xue，“Graph Transformations on CDFG for Granularity Selection in Hardware-Software Partitioning: Experiments and Analysis”，8th International Conference on CAD/Graphics，OCT 29-31，2003 CAD/ GRAPHICS TECHNOLOGY AND ITS APPLICATIONS，PROCEEDINGS，CAD/Graphicsu201903，Macau 2003.10. 303-308，ISTP BAY65 000224243000046 Weimin Wu，Zhuoyuan Li，Hanbin Zhou，Xianlong Hong，Jinian Bian，“A Size-Balancing Approach to Mixed Mode Placement”，8th International Conference on CAD/Graphics，OCT 29-31，2003 CAD/ GRAPHICS TECHNOLOGY AND ITS APPLICATIONS，PROCEEDINGS，CAD/Graphicsu201903，Macau 2003.10. 309-314，ISTP BAY65 000224243000047 Qiang Wu，Jinian Bian，Hongxi Xue，Yiping Fan，Weimin Wu，Xianlong Hong and Jun Gu，“Applying Search Space Smoothing Technique to Hardware/Software Partitioning”，Proceedings of 2003 5th International Conference on ASIC. (IEEE Cat. No.03TH8690)，ASICONu201903，Beijing 2003.10，85-88，ISTP BY56E 000189408900012，INSPEC 8015734，IEEE xplore Hu Heng，Hongxi Xue，Jinian Bian，“A heuristic state assignment algorithm for Post-Layout Re-synthesis”，Proceedings of 2003 5th International Conference on ASIC. (IEEE Cat. No.03TH8690)，ASICONu201903，Beijing 2003.10. 136-139 ISTP BY56E 000189408900024，INSPEC 8015745，IEEE xplore Wang Yunfeng，Bian Jinian，Wu Qiang，Hu Heng，“Reallocation and Rescheduling after Floor-planning for Timing Optimization”，Proceedings of 2003 5th International Conference on ASIC. (IEEE Cat. No.03TH8690)，ASICONu201903，Beijing 2003.10. 212-215 ISTP BY56E 000189408900042，INSPEC 8015761，IEEE xplore Ming Zhu，Jinian Bian，Weimin Wu，Hongxi Xue，“Property-Classified Hybrid Verification based on CDFG”，Proceedings of 2003 5th International Conference on ASIC. (IEEE Cat. No.03TH8690)，ASICON03，Beijing 2003.10. 233-237 ISTP BY56E 000189408900047，INSPEC 8015766，IEEE xplore Jin Chen，Qiang Wu，Jinian Bian，Hongxi Xue，“SGA - A Self-adaptable granularity Approach for Hardware/Software Co-design”P(pán)roceedings of 2003 5th International Conference on ASIC. (IEEE Cat. No.03TH8690)，ASICONu201903，Beijing 2003.10. 365-368 ISTP BY56E 000189408900079，INSPEC 8015794，IEEE xplore Yang Xiao，Yufeng Wang，Jinian Bian，“Placement-Aware Retiming and Rescheduling in High-Level Synthesis”，CAID/CDu201903，Hangzhou 2003.10. 556-561 Qiang Wu，Jinian Bian，Hongxi Xue，“A Unified Method for System Synthesis with Hardware and Software IP Cores in SoC Design”，CAID/CDu201903，Hangzhou 2003.10. 802-807 Weimin Wu，Di Wang，Weiwei Zheng，Jinian Bian，Ming Zhu，“Property Checking Using RTL ATPG”，CAID/CDu201903，Hangzhou 2003.10. 871-875 2002 Zhu Ming，Bian Jinian，Xue Hongxi，“Uniform Internal Model for Hybrid Language Description for Logic Re-synthesis after Placement”，CAID&CDu201901，jinan，qingdao 2001.10. 647-651 Wang yunfeng，Lu Feng，Bian Jinian，Xue Hongxi，“，Merging High-Level Based on OBDD and Circuit Structure”，International Conference on ASIC，Proceedings，ASICONu201901，Shanghai 2001. 10，190-193，EI 02126890572，ISTP BU56Q 0001 76369900036，INSPEC 7260694，IEEE xplore Yang Xun，Zhu Ming，Xue Hongxi，Bian Jinian，Hong Xianlong，“A Platform for System-on-a-chip Design Prototyping”，2001 4th International Conference on ASIC Proceedings，ASICONu201901，Shanghai 2001. 10. 781-784，EI 02126890717，ISTP BU56Q 0001 76369900184，INSPEC 7260842，IEEE xplore Liu Jianhua，Zhu Ming，Bian Jinian，Xue Hongxi，“A debug sub-system for embedded-system co-verification”，2001 4th International Conference on ASIC Proceedings，ASICONu201901，Shanghai 2001.10.，777-780，EI 02126890716，ISTP BU56Q 0001 76369900183，INSPEC 7260841，IEEE xplore 2000 Yang Xun，Xue Hongxi，Bian Jinian，“A Platform Supporting Hw/Sw System Coverification”，CAID&CD 2000，Hong Kong 2000.11. 533-536 Yiping Fan，Jinsong Bei，Jinian Bian，HongXi Xue，Xianlong Hong，Jun Gu，“VERIS: An Efficient Model Checker for Synchronous VHDL Designs”，WCC 2000 (icda 2000) 2000.8. 475-480; Annual International Hardware Description Language Conference and Exhibition (HDLCON)，AUG，2000; System-On-Chip Methodologies & Design Languages 2001，97-107，ISTP BT43U 000173022800009 Jinian Bian，Hongxi Xue，Yanqing Wu，“OMDD - New Representation of Boolean Functions Oriented to Logic Synthesis”，Procedings Volume VII. Computer Science and Engineering: Part I. Programming-Techniques，SCI2000/ISAS2000，Orlando，F(xiàn)lorida，USA 2000.7. Xun Yang，Hongxi Xue，Jinian Bian，“The Integration of Simulation and Emulation for SOC HW/SW Coverification”，Procedings Volume VIII. Computer Science and Engineering: Part II Geographical Information Systems，SCI2000/ISAS2000，Orlando，F(xiàn)lorida，USA 2000.7. Wangning Long，Yu-Liang Wu，Jinian Bian，“IBAW: An Implication-Tree Based Alternative-Wiring Logic Transformation”，1999 IEEE International Symposium on Intelligent Signal Processing and Communication Systems. Signal Processing Used to Accelerate VHDL Simulation”，APCHDL’99，F(xiàn)ukuoka，Japan 1999.10. 17-21 Jinsong Bei，Hongxing Li，Jinian Bian，Hongxi Xue，Xianlong Hong，“FSM modeling of synchronous VHDL design for symbolic model checking”，Proceedings of the ASP-DAC ’99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)，ASP-DACu201999，Hong Kong，1999.1. 363-366，ISTP BM69S 000079494700090，INSPEC 6358324，IEEE xplore 1998 Jinsong Bei，Jinian Bian，HongXi Xue，Wangning Long，“A new heuristic algorithm”，5th International Conference on Computer-Aided Design and Computer Graphics，CAD/Graphics’97，Shenzhen 1997.12. 601-604 ISTP BK32T 000071822600126 Jinian Bian，Hongxi Xue，Ming Su. “VIDE: A visual VHDL integrated design environment”，Proceedings of the ASP-DAC ’97. Asia and South Pacific Design Automation Conference 1997 (Cat. No.97TH8231)，ASP-DAC’97，Chiba，Japan 1997.1，383-386，EI 97073722182，ISTP BJ06S，INSPEC 5559025，IEEE xplore 1995 Bian Jinian，Lu Feng，Wan Bo，Su Ming，“A model and an algorithm in visual VHDL and its implementation”，1995 4th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.95TH8143)，ICSICT’95，Beijing 1995.10. 361-363，EI 96063224076，ISTP 1996 No7，P67258，INSPEC 5340929，IEEE xplore 1991 Bian Jinian，Liu Yu. “Signal state and delay calculation”，China 1991 International Conference on Circuits and Systems. Conference Proceedings (Cat. No.91TH0387-1)，ICCAS’91，Shenzhen，1991.6. 917-920，EIM 9305-026040，EI 93030727787 ，INSPEC 4264542，IEEE xplore學(xué)術(shù)職務(wù)
中國(guó)計(jì)算機(jī)學(xué)會(huì) 高級(jí)會(huì)員 中國(guó)計(jì)算機(jī)學(xué)會(huì) 計(jì)算機(jī)輔助設(shè)計(jì)與圖形學(xué)專(zhuān)業(yè)委員會(huì) 副主任 中國(guó)計(jì)算機(jī)學(xué)會(huì)會(huì)刊《計(jì)算機(jī)輔助設(shè)計(jì)與圖形學(xué)學(xué)報(bào)》副主編 著作和譯作 1. 邊計(jì)年等譯：實(shí)用C語(yǔ)言FPGA設(shè)計(jì)，機(jī)械工業(yè)出版社，待出版 2. 邊計(jì)年，薛宏熙 等譯：用SpecC進(jìn)行系統(tǒng)設(shè)計(jì)，清華大學(xué)出版社，待出版 3. 邊計(jì)年，薛宏熙，蘇 明，吳為民：數(shù)字系統(tǒng)設(shè)計(jì)自動(dòng)化（第2版），清華大學(xué)出版社，2005.7. 4. 邊計(jì)年，吳為民 等譯：嵌入式系統(tǒng)的規(guī)范與設(shè)計(jì)，機(jī)械工業(yè)出版社，2005.7. 5. 邊計(jì)年，薛宏熙，吳 強(qiáng) 譯：數(shù)字邏輯與VHDL設(shè)計(jì)，清華大學(xué)出版社，2005.1. 6. 邊計(jì)年，薛宏熙 譯：用VHDL設(shè)計(jì)電子線路，清華大學(xué)出版社，2000.8. 7. 洪先龍，劉偉平，邊計(jì)年 等著：超大規(guī)模集成電路計(jì)算機(jī)輔助設(shè)計(jì)技術(shù)，國(guó)防工業(yè)出版社，1998.6. 8. 喬長(zhǎng)閣，邊計(jì)年，薛宏熙 譯：VHDL簡(jiǎn)明教程，清華大學(xué)出版社，1997.10. 9. 薛宏熙，邊計(jì)年，蘇 明：數(shù)字系統(tǒng)設(shè)計(jì)自動(dòng)化，清華大學(xué)出版社，1996.10. 10. 吳文虎主編：中小學(xué)計(jì)算機(jī)知識(shí)詞典，天津科技出版社，1994.9.（副主編） 11. 譚浩強(qiáng)主編：微型計(jì)算機(jī)實(shí)用手冊(cè)，高等教育出版社，1993.4.（第二分冊(cè)編委） 12. 薛宏熙，邊計(jì)年，趙致格：數(shù)字系統(tǒng)計(jì)算機(jī)輔助設(shè)計(jì)，海洋出版社 1990.6. 13. 吳文虎，邊計(jì)年（執(zhí)筆）：中學(xué)計(jì)算機(jī)教程(下冊(cè))，清華大學(xué)出版社 1987. 14. 唐澤圣，周嘉玉 等譯：交互式計(jì)算機(jī)圖形學(xué)基礎(chǔ)，清華大學(xué)出版社 1986.11.
